Capacitor having a structure capable of restraining deterioration of dielectric film, semiconductor device having the capacitor and method of manufacturing the same

ABSTRACT

Disclosed is a semiconductor device having a structure capable of restraining deterioration of a dielectric film (BSTO) of a capacitor even when annealing is performed in a hydrogen-containing atmosphere. This semiconductor device comprises a plurality of dispersion electrodes (SRO) formed in a dispersed manner above a semiconductor substrate, and a common electrode commonly facing the dispersion electrodes via respective dielectric films (BSTO). This common electrode includes a lower conductive layer (SRO) formed on the dielectric films, a barrier layer (Al 2 O 3 ) formed on the lower conductive layer and an upper conductive layer (Al) formed on the barrier layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 11-173018, filed Jun. 18,1999, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to the structure of a capacitor,and, more particularly, to suppression of the deterioration of acapacitor originated from the deterioration of a dielectric film whichconstitutes a capacitor film.

[0003] As the microfabrication of semiconductor devices such as DRAM andFRAM progresses, the. cell area becomes smaller, making it difficult tosecure the capacitance of capacitors that is demanded for storing data.

[0004] As one solution to this problem, in the case of DRAMs, forexample, an attempt has been considered which gains a greatercapacitance for the same capacitor area by using a high-dielectricsubstance such as BSTO having a higher dielectric constant than that ofa silicon oxide film or silicon nitride film, which has conventionallybeen used as a capacitor film.

[0005] The fabrication of semiconductor devices requires that annealingin a hydrogen-containing atmosphere (hereinafter called “hydrogenannealing”) after a multi-layer interconnection step in order toeliminate a plasma damage caused by the multi-layer interconnection stepafter forming a capacitor, thereby providing excellent transistorcharacteristics and leak characteristic. This hydrogen annealing is alsocalled “sintering”.

[0006] It however became apparent that high-dielectric substances suchas BSTO, or ferroelectric substances such as PZT have a low resistanceto hydrogen annealing so that hydrogen annealing significantlydeteriorates their film qualities. One possible cause for thisdeterioration is that hydrogen works as a reducing agent to reduce BSTOor PZT containing oxygen in hydrogen annealing.

[0007] This deterioration of a dielectric film which constitutes acapacitor film is likely to degrade the capacitor characteristics.

BRIEF SUMMARY OF THE INVENTION

[0008] Accordingly, it is a primary object of the present invention toprovide a capacitor whose structure is capable of restraining thedeterioration of a dielectric film even when annealing is performed in ahydrogen-containing atmosphere, and a semiconductor device having thiscapacitor.

[0009] It is another object of the present invention to provide asemiconductor device having a circuit structure which can suppress thedeterioration of a data retaining characteristic.

[0010] To achieve the first object, according to one aspect of thisinvention, there is provided a semiconductor device comprising:

[0011] one electrode formed above a semiconductor substrate; and

[0012] an opposing electrode facing the one electrode via a dielectricfilm and including a lower conductive layer formed on the dielectricfilm, a barrier layer formed on the lower conductive layer and an upperconductive layer formed on the barrier layer.

[0013] In this semiconductor device, the opposing electrode includes thelower conductive layer, the barrier layer and the upper conductivelayer. This opposing electrode faces the one electrode via thedielectric film and is one constituting element of a capacitor. variousmaterials can be selected for the barrier layer included in the oneelectrode, regardless of the insulating property and the conductivity.For example, using a reducing material or a material which has a finefilm quality for the barrier layer can reduce the amount of the reducingagent that reaches the dielectric film. Even if a material whose filmquality is deteriorated by reduction is used for the dielectric film,therefore, the degradation of the dielectric film can be restrained.Even when annealing is performed in an atmosphere containing a reducingagent, therefore, it is possible to suppress the degradation of thedielectric film.

[0014] To achieve the second object, according to another aspect of thisinvention, there is provided a semiconductor device comprising:

[0015] memory cells each having a cell capacitor which includes astorage electrode and a plate electrode facing the storage electrode viaa dielectric film;

[0016] a circuit for generating a potential to be applied to the plateelectrode; and

[0017] a capacitor connected in series between an output terminal of thecircuit and the plate electrode.

[0018] This semiconductor device has the capacitor connected in seriesbetween the output terminal of the circuit, which generates a potentialto be applied to the plate electrode, and the plate electrode. Thiscapacitor absorbs noise which is produced by memory cells at the time ofdata access. This makes it hard for that noise to go outside.

[0019] The capacitor also absorbs noise which is produced outside thememory cells. This makes it difficult for that noise to reach the plateelectrode, thereby suppressing the deterioration of the data retainingcharacteristic that is originated from the noise applied to the plateelectrode.

[0020] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0021] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0022]FIG. 1 is a diagram showing a capacitor structure according to afirst embodiment of this invention;

[0023]FIG. 2 is a diagram depicting a DRAM cell array according to thefirst embodiment of this invention;

[0024]FIG. 3A is an equivalent circuit diagram of a DRAM cell array whena barrier layer has an insulating property;

[0025]FIG. 3B is an equivalent circuit diagram of a DRAM cell array whenthe barrier layer has a conductivity;

[0026]FIG. 4 is a diagram illustrating an FRAM cell array which uses thecapacitor structure according to the first embodiment of this invention;

[0027]FIG. 5A is an equivalent circuit diagram of an FRAM cell arraywhen a barrier layer has an insulating property;

[0028]FIG. 5B is an equivalent circuit diagram of an FRAM cell arraywhen the barrier layer has a conductivity;

[0029]FIG. 6A is a plan view of a DRAM cell array according to a secondembodiment of this invention;

[0030]FIG. 6B is a cross-sectional view taken along the line 6B-6B inFIG. 6A;

[0031]FIGS. 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H and 7I are cross-sectionalviews illustrating a DRAM according to the second embodiment of thisinvention step by step of main fabrication steps;

[0032]FIG. 8 is a cross-sectional view of a DRAM according to amodification of the second embodiment of this invention;

[0033]FIG. 9 is a cross-sectional view showing a DRAM according to athird embodiment of this invention;

[0034]FIGS. 10A, 10B, 10C, 10D, 10E, 10F, 10G and 10H arecross-sectional views illustrating a DRAM according to the thirdembodiment of this invention step by step of main fabrication steps;

[0035]FIG. 11 is a cross-sectional view showing a DRAM according to afourth embodiment of this invention;

[0036]FIGS. 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, 12I, 12J, 12K and12L are cross-sectional views illustrating a DRAM according to thefourth embodiment of this invention step by step of main fabricationsteps;

[0037]FIG. 13A is a cross-sectional view of a concave stacked capacitor;

[0038]FIG. 13B is a cross-sectional view of a convex stacked capacitor;

[0039]FIG. 13C is a cross-sectional view of a cylindrical stackedcapacitor;

[0040]FIG. 13D is a cross-sectional view of a planar capacitor;

[0041]FIG. 13E is a cross-sectional view of a stacked gate transistor;and

[0042]FIGS. 14A and 14B are circuit diagrams each showing connectionbetween a plate potential generating circuit and a plate electrode.

DETAILED DESCRIPTION OF THE INVENTION

[0043] Preferred embodiments of the present invention will now bedescribed with reference to the accompanying drawings. In the followingdescription, like or same reference numerals are given to correspondingcomponents in the drawings.

[0044] (First Embodiment)

[0045]FIG. 1 is a diagram showing a capacitor structure according to thefirst embodiment of this invention.

[0046] As shown in FIG. 1, the capacitor structure 1 according to thefirst embodiment of this invention has a plurality of dispersionelectrodes 2 dispersed, and a common electrode 4 common to thosedispersion electrodes 2. The common electrode 4 faces the dispersionelectrodes 2 via respective capacitor films (dielectric films) 3. Thecommon electrode 4 has a lamination structure comprised of at leastthree layers, namely a lower conductive layer 5, a barrier layer 6 andan upper conductive layer 7. The lower conductive layer 5 faces thedispersion electrodes 2 via the respective capacitor films 3. The upperconductive layer 7 faces the lower conductive layer 5 via the barrierlayer 6.

[0047]FIG. 2 is a diagram depicting a 1-transistor-1-capacitor type DRAMcell array which has the capacitor structure 1 according to the firstembodiment.

[0048] As shown in FIG. 2, the DRAM cell array has an array of celltransistors CT. The cell transistors CT have gates which serve as wordlines WL (WL1, WL2), drains Dc connected to bit lines BL (BL1, BL2), andsources Sc connected to the respective dispersion electrodes 2. Thedispersion electrodes 2 face the common electrode 4 via the respectivecapacitor films 3. A plate potential VPL is generated from a platepotential generating circuit 11 and supplied to the common electrode 4.As a result, the common electrode 4 functions as a plate electrode, andthe dispersion electrodes 2 as storage electrodes.

[0049]FIG. 3A is a diagram showing an equivalent circuit of a DRAM cellarray when the barrier layer 6 has an insulating property, and FIG. 3Bis a diagram showing an equivalent circuit of a DRAM cell array when thebarrier layer 6 has a conductivity.

[0050] As shown in FIG. 3A, when the barrier layer 6 has an insulatingproperty, the source Sc of each cell transistor CT is connected to theplate potential generating circuit 11 via two capacitors Cc and Cp thatare connected in series to each other. The plate potential VPL issupplied from the upper conductive layer 7 of the capacitor Cp to thelower conductive layer 5 common to the capacitors Cc and Cp by, forexample, capacitive coupling. Accordingly, the capacitor Cc which iscomprised of the dispersion electrode 2, the capacitor film 3 and thelower conductive layer 5 serves as a cell capacitor and chargesaccording to data are stored in the capacitor film 3.

[0051] As shown in FIG. 3B, when the barrier layer 6 has a conductivity,the source Sc of each cell transistor CT is connected to the platepotential generating circuit 11 via a resistor Rp and a capacitor Ccthat are connected in series to each other. The plate potential VPL issupplied from the upper conductive layer 7 to the lower conductive layer5 of the capacitor Cc via the resistor Rp comprised of the barrier layer6. Accordingly, as in the previous case where the barrier layer 6 has aninsulating property, the capacitor which is comprised of the dispersionelectrode 2, the capacitor film 3 and the lower conductive layer 5serves as a cell capacitor and charges according to data are stored inthe capacitor film 3.

[0052]FIG. 4 is a diagram illustrating a 1-transistor-1-capacitor typeFRAM cell array which uses the capacitor structure 1 according to thefirst embodiment.

[0053] As shown in FIG. 4, the FRAM cell array has an array of celltransistors CT. The cell transistors CT have gates which serve as wordlines WL (WL1, WL2), sources connected to bit lines BL (BL1, BL2), anddrains connected to the respective dispersion electrodes 2.

[0054] In the case where the FRAM uses a driving pulse in reading andwriting data, the common electrode is separated into common electrodes4-1 and 4-2 for the respective word lines WL, for example. Thedispersion electrodes 2 face the common electrodes 4-1 and 4-2 via thecapacitor films 3. A driving pulse DP1 is supplied to the upperconductive layer, 7-1, of the common electrode 4-1 from a driving pulseline driver (the driving pulse line is also called “plate line”) 12, anda driving pulse DP2 is supplied to the upper conductive layer, 7-2, ofthe common electrode 4-2 from the driving pulse line driver 12.

[0055]FIG. 5A is a diagram showing an equivalent circuit of an FRAM cellarray when the barrier layer 6 has an insulating property, and FIG. 5Bis a diagram showing an equivalent circuit of an FRAM cell array whenthe barrier layer 6 has a conductivity.

[0056] As shown in FIG. 5A, when the barrier layer 6 has an insulatingproperty, the source Sc of each cell transistor CT is connected to thedriving pulse line driver 12 via two capacitors Cc and Cp that areconnected in series to each other. The driving pulse DP1 is suppliedfrom the upper conductive layer 7-1 of the capacitor Cp to the lowerconductive layer 5 common to the capacitors Cc and Cp by, for example,capacitive coupling. Accordingly, the capacitor Cc which is comprised ofthe dispersion electrode 2, the capacitor film 3 and the lowerconductive layer 5 serves as a cell capacitor and the capacitor film 3is polarized according to data.

[0057] As shown in FIG. 5B, when the barrier layer 6 has a conductivity,the source Sc of each cell transistor CT is connected to the drivingpulse line driver 12 via a resistor Rp and a capacitor Cc that areconnected in series to each other. The driving pulse DP1 is suppliedfrom the upper conductive layer 7 to the lower conductive layer 5 of thecapacitor Cc via the resistor Rp comprised of the barrier layer 6.Accordingly, as in the previous case where the barrier layer 6 has aninsulating property, the capacitor which is comprised of the dispersionelectrode 2, the capacitor film 3 and the lower conductive layer 5serves as a cell capacitor and the capacitor film 3 is polarizedaccording to data.

[0058] As apparent from the above, the capacitor film 3 having thecapacitor structure 1 can be used as a dielectric substance of a cellcapacitor or a dielectric substance for retaining data in a DRAM orFRAM. In this respect, a high-dielectric substance and ferroelectricsubstance are preferably 7 used for the capacitor film 3. According tothis invention, particularly preferable high-dielectric substances andferroelectric substances include (Ba,Sr)TiO₃ (generally, BSTO), BaTiO₃,SrTiO₃, Ta₂O₅, Pb(Zr,Ti)O₃ (generally, PZT), Pb(Nb,Ti)O₃, PbZrO₃,LiNbO₃, SrBi₂Ta₂O₉, SrBi₂(Ta,Nb)₂O₉ and Bi₄Ti₃O₁₃.

[0059] Those preferable materials are oxides all of which have a lowresistance to hydrogen annealing.

[0060] According to this invention, therefore, a reducing material or amaterial which hardly passes hydrogen is used for the barrier layer 6.The following is a list of materials having such a property:

[0061] An example of a preferable reducing material is a metal oxidewhich contains at least one of metals Al, W, Cu, Ti, Co, Ta, Nb, Ru andIr.

[0062] One example of a preferable material which hardly passes hydrogenis a silicon nitride.

[0063] The following may be the reasons why the film that contains oneof the aforementioned materials suppresses a damage caused by hydrogenannealing.

[0064] (1) In the Case of Metal Oxide

[0065] At the time hydrogen annealing is performed, not only thecapacitor film 3 but also its metal oxide is reduced. Consequently, theamount of hydrogen that reaches the capacitor film 3 decreases, thussuppressing a reduction-originated damage of the capacitor film 3.Excessive oxygen, if contained in the metal oxide, combines withhydrogen. The amount of the hydrogen reaching the capacitor film 3decreases further. This suppresses the reducing damage to the capacitorfilm 3.

[0066] (2) In the Case of Silicon Nitride

[0067] As the film is minute, it hardly passes hydrogen. As in the caseof a metal oxide, therefore, the amount of hydrogen that reaches thecapacitor film 3 decreases, thus suppressing a reduction-originateddamage of the capacitor film 3.

[0068] According to the capacitor structure 1 of the first embodiment,the common electrode 4 has a lamination structure comprised of at leastthree layers which are the lower conductive layer 5, the barrier layer 6and the upper conductive layer 7. Using a reducing material or amaterial which hardly passes hydrogen for the barrier layer 6 in thethree-layer structure can suppress the deterioration of the film qualityof the capacitor film 3 even when hydrogen annealing is carried out.

[0069] An example of a preferable material for the lower conductivelayer 5 is a conductive material which contains at least one of metalsPt, Ru, Re, Os, Rh, Ir, Fe, Mn, Cr, Co, Ni and Ti, or a metal oxidewhich contains at least one of those metals, or an alloy of at least oneof those metals and at least one of alkaline earth metals, or an oxideof an alloy of at least one of those metals and at least one of alkalineearth metals, or an alloy of at least one of those metals and at leastone of rare earth metals, or an oxide of an alloy of at least one ofthose metals and at least one of rare earth metals.

[0070] An example of a preferable material for the upper conductivelayer 7 is a conductive material which contains at least one of metalsAl, W, Cu, Ti, Co, Ta and Nb, or a compound which contains at least oneof those metals, or an alloy which contains at least one of thosemetals, or a compound of an alloy which contains at least one of thosemetals.

[0071] When the lower conductive layer 5, the barrier layer 6 and theupper conductive layer 7 constitute the capacitor Cp, it is desirablethat the capacitance of the capacitor Cp be larger than that of thecapacitor Cc which is comprised of the lower conductive layer 5, thecapacitor film 3 and the dispersion electrode 2.

[0072] When the capacitance of the capacitor Cp is smaller than that ofthe capacitor Cc, for example, the lower conductive layer 5 may becoupled to the dispersion electrode 2 so that the potential of the lowerconductive layer 5 varies in accordance with a change in the potentialof the dispersion electrode 2. This makes it difficult to charge orpolarize the capacitor film 3.

[0073] Such a situation can be improved by making the capacitance of thecapacitor Cp greater than that of the capacitor Cc.

[0074] Further, it is desirable that the electrical resistivity of theupper conductive layer 7 be lower than that of the lower conductivelayer 5 and that of the barrier layer 6. Making the electricalresistivity of the upper conductive layer 7 lower than that of the lowerconductive layer 5 and that of the barrier layer 6 reduces theresistance of the common electrode 4 itself. The reduced resistance ofthe common electrode 4 can permit the potential of the common electrode4 to be effectively applied to the entire dispersion electrode 2.

[0075] Some of specific examples wherein the capacitor structure 1according to this invention is adapted to a semiconductor memory,particularly, to a stacked DRAM, will be discussed as other embodimentsone by one.

[0076] (Second Embodiment)

[0077]FIG. 6A is a plan view of a DRAM cell array according to thesecond embodiment of this invention, and FIG. 6B is a cross-sectionalview showing the cross sections of the DRAM cell array according to thesecond embodiment and a peripheral circuit of the DRAM. The crosssection of the DRAM cell array in FIG. 6B is taken along the line 6B-6Bin FIG. 6A and shows a portion where the storage electrode appears. Thecross section of the DRAM peripheral circuit in FIG. 6B shows a portionwhere the plate electrode in the peripheral circuit appears.

[0078] The DRAM shown in FIGS. 6A and 6B together with its manufacturingmethod will be discussed below.

[0079]FIGS. 7A through 7I are cross-sectional views illustrating theDRAM according to the second embodiment of this invention step by stepof main fabrication steps.

[0080] First, the structure that is shown in FIG. 7A is constructed byusing a known method. The following exemplifies how to form thatstructure. As shown in FIG. 7A, device isolation regions 41 are formedin a silicon substrate 40 and device regions 42 where active elementsare to be formed are defined on the silicon substrate 40. Next, gateelectrodes 43 are formed on the silicon substrate 40 and thensource/drain regions 44 are formed in the respective device regions 42.As a result, cell transistors CT are formed in the cell array portionshown in FIGS. 6A and 6B, and peripheral transistors PT are formed inthe peripheral circuit portion. The gate electrodes 43 of the celltransistors CT are word lines WL. Each gate electrode 43 is formed of alamination film comprised of conductive polysilicon and a high-meltingpoint metal silicide. Next, a first interlayer insulating film 45-1 isformed and contact holes 46-1 which are connected to the associatedsource or drain regions 44 and interconnection holes 46-2 are formed inthe first interlayer insulating film 45-1. Then, interconnection layers47 are formed in the holes 46-1 and 46-2. The interconnection layers 47are formed by a lamination film comprising, for example, titaniumnitride (TiN) and titanium (Ti). The interconnection layer 47 shown onthe left-hand side in FIG. 6B indicates that of the lines for theperipheral circuit for which the same layer as the bit lines BL is used.Then, a second interlayer insulating film 45-2 is formed. Then, contactholes 48 which are connected to the other ones of the source/drainregions 44 are formed in the first interlayer insulating film 45-1 andthe second interlayer insulating film 45-2. Next, a contract plug 49 isformed in each contact hole 48.

[0081] As shown in FIG. 7B, a third interlayer insulating film 45-3 isformed on the second interlayer insulating film 45-2. where the contactplugs 49 are exposed. Then, openings 50 for forming cell capacitors areformed in the third interlayer insulating film 45-3 by usingphotolithography and RIE.

[0082] Next, as shown in FIG. 7C, a conductor such as SrRuO₃(hereinafter referred to as “SRO”) is deposited on the third interlayerinsulating film 45-3 where the openings 50 are formed, thereby formingan SRO film. Then, those portions of the SRO film which exclude what islocated in the openings 50 are removed by using CMP, for example. As aresult, storage electrodes 2 of the SRO film are formed in the openings50. The storage electrodes 2 are connected to the other ones of thesource/drain regions 44 via the respective contact plugs 49.

[0083] Next, a high-dielectric substance such as BSTO or a ferroelectricsubstance is deposited on the storage electrodes 2 and the thirdinterlayer insulating film 45-3, thus forming the capacitor film 3 asshown in FIG. 7D. If the capacitor film 3 is made of BSTO, it is desiredthat the film 3 be about 20 nm thick. If the film 3 is made of Ta₂O₅, itis desirable that the film 3 be about 10 nm to 15 nm thick. Then, aconductor such as SRO is deposited on the capacitor film 3, therebyforming the lower conductive layer 5.

[0084] Next, alumina (Al₂O₃) or the like is deposited on the lowerconductive layer 5 to thereby form the barrier layer 6 as shown in FIG.7E. When the barrier layer 6 has an insulating property, it is desirablethat its thickness be about 1 nm to 50 nm. When the barrier layer 6 isof alumina, particularly, the thickness should desirably be about 5 nm.To form an alumina film as thin as about 5 nm, aluminum should besputtered in an atmosphere containing, for example, oxygen.

[0085] Then, a conductor such as aluminum is deposited on the barrierlayer 6 by sputtering, thus forming the upper conductive layer 7, asshown in FIG. 7F.

[0086] Next, the upper conductive layer 7, the barrier layer 6 and thelower conductive layer 5 are etched at a time by using photolithographyand RIE, thus forming the plate electrode 4 as shown in FIG. 7G.Accordingly, the plate electrode 4 formed has a three-layer structure ofthe lower conductive layer 5, the barrier layer 6 and the upperconductive layer 7.

[0087] Then, a fourth interlayer insulating film 45-4 is formed on thethird interlayer insulating film 45-3 on which the plate electrode 4 isformed, as shown in FIG. 7H. Next, contact holes 51 which are connectedto the upper conductive layer 7 and contact holes 52 which are connectedto the interconnection layer 47 are formed in the fourth interlayerinsulating film 45-4 by using photolithography and RIE.

[0088] Next, as shown in FIG. 7I, titanium nitride (TiN) and titanium(Ti) are sequentially deposited on the fourth interlayer insulating film45-4 where the contact holes 51 and 52 are formed, thus forming a TiN/Tilamination film. Then, those portions of this lamination film whichexclude the contact holes 51 and 52 are removed. As a result, contactplugs 53 and 54 of the TiN/Ti lamination film are respectively formed inthe contact holes 51 and 52.

[0089] Then, as shown in FIG. 6B, titanium nitride (TiN) and titanium(Ti) are sequentially deposited on the fourth interlayer insulating film45-4 where the contact plugs 53 and 54 are formed, thus forming a TiN/Tilamination film. Then, this lamination film is removed by usingphotolithography and RIE, thus forming interconnection layers 55 and 56.

[0090] Thereafter, though not illustrated particularly, further multipleinterconnection layers are formed and a passivation film of siliconnitride or silicon dioxide is formed finally. Then, hydrogen annealingis performed to adjust the characteristics of the cell transistors CTand the characteristics of the peripheral transistors PT, whichcompletes the DRAM according to the second embodiment.

[0091] According to the DRAM of the second embodiment, the plateelectrode 4 has a three-layer structure of the lower conductive layer 5,(SRO), the barrier layer 6 (Al₂O₃) and the upper conductive layer 7(Al). Even if hydrogen annealing is carried out after a multi-layerinterconnection step, the barrier layer 6 (Al₂O₃) protects the capacitorfilm 3 (BSTO) against a reduction-originated damage. It is thereforepossible to suppress the degradation of the film quality of thecapacitor film 3 and prevent the degradation of the capacitorcharacteristics, such as an increase in leak current.

[0092] According to the second embodiment, sputtering is used as adeposition method for the barrier layer 6.

[0093] For the generation of, for example, the 0.15-μm rule, the minimumwidth of the openings 50 where capacitors are formed is approximately0.15 μm. Depositing the storage electrode 2, the capacitor film 3 andthe lower conductive layer 5 in such an opening 50 by, for example,about 0.02 μm, 0.02 μm and 0.04 μm respectively, mostly buries theopening 50. Particularly, the top surface of the lower conductive layer5 becomes almost planarized.

[0094] If the total film thickness of the storage electrode 2, thecapacitor film 3 and the lower conductive layer 5 is set equal to orgreater than twice the minimum width of the opening 50, the top surfaceof the lower conductive layer 5 can be planarized. The planarization ofthe top surface of the lower conductive layer 5 eliminates the need forusing such a method, which is excellent in a step coverage property, informing the barrier layer 6. It is therefore possible to provide astructure to which, for example, sputtering can be used suitably.

[0095] Of course, instead of sputtering, a scheme which has a betterstep coverage property, such as CVD or spin coating, may be used to formthe barrier layer 6.

[0096] According to the second embodiment, a conductive oxide whichgenerally has a high electrical resistivity, such as SRO, is used forthe lower conductive layer 5. In this case, it is desirable that aconductor whose electrical resistivity is lower than that of the lowerconductive layer 5, e.g., aluminum, be used for the upper conductivelayer 7. This can allow the plate potential VPL to be applied to theentire cell array having a wide area more effectively.

[0097] According to the second embodiment, the plate potential VPL issupplied to the upper conductive layer 7 and the barrier layer 6 isformed of a material having an insulating property, e.g., alumina. Anequivalent circuit in this case is illustrated in FIG. 3A. The structureshown in FIG. 3A has a capacitor connected in series between theterminal for supplying the plate potential VPL and the cell capacitor,thereby reducing the effective cell capacitance.

[0098] In an ordinary DRAM, the plate electrode 4 is commonly used formultiple cells (typically, 256 kbits) and has a very large pattern. As aspecific example, the area of the plate electrode 4 is approximately48,000 μm² for the generation of, for example, the 0.15-μm rule. In thiscase, if alumina of 5 nm in thickness is used for the barrier layer 6,the capacitance becomes about 7×10⁵ fF. The capacitance per one bit ofcell capacitor is normally about 30 fF. Even if a capacitor of about7×10⁵ fF is connected in series, therefore, a reduction in thecapacitance per one bit of cell capacitor is equal to or less than0.01%, small enough to be negligible.

[0099] To increase the capacitance of the capacitor having the barrierlayer 6 used as the dielectric layer, it is desirable to make thebarrier layer 6 thinner than the capacitor film 3.

[0100] According to the second embodiment, aluminum is used for theupper conductive layer 7 and a TiN/Ti lamination film is used for thecontact plug 53. Such a combination of aluminum and TiN easily achievesan excellent ohmic contact at the bottom of the contact plug 53.

[0101] The barrier layer 6 may be made conductive. An equivalent circuitin this case is illustrated in FIG. 3B. As one way of making the barrierlayer 6 conductive is to reduce the amount of oxygen in, for example,alumina to a value lower than the stoichiometric ratio or Al₂O_(3−d)(d>0). In the case where the barrier layer 6 is provided with aconductivity, if the barrier layer 6 merely has a high electricalresistivity or it merely has a slight conductivity, the resistancebetween the upper conductive layer 7 and the lower conductive layer 5becomes sufficiently low. This is because the plate electrode 4 has avery large area as mentioned above. When the barrier layer 6 is providedwith a conductivity, therefore, a reduction in cell capacitance can besuppressed.

[0102] A modification of the second embodiment will now be discussed.

[0103]FIG. 8 is a cross-sectional view showing a DRAM according to amodification of the second embodiment of this invention.

[0104] As shown in FIG. 8, each contact hole 51 may be formed throughboth the upper conductive layer 7 so that the barrier layer 6 and thecontact plug 53 directly contacts the lower conductive layer 5.

[0105] As the contact plug 53 directly contacts the lower conductivelayer 5, this modification has an advantage of suppressing a reductionin cell capacitance as in the case where the barrier layer 6 is providedwith a conductivity.

[0106] It should be noted that the contact hole 51 can be formed easilyif the barrier layer 6 is thinner than the capacitor film 3.

[0107] (Third Embodiment)

[0108]FIG. 9 is a cross-sectional view showing the cross sections of aDRAM cell array according to the third embodiment and a peripheralcircuit of the DRAM.

[0109] The DRAM according to the third embodiment illustrated in FIG. 9together with its manufacturing method will be described below.

[0110]FIGS. 10A through 10H are cross-sectional views illustrating theDRAM according to the third embodiment of this invention step by step ofmain fabrication steps.

[0111] First, as shown in FIG. 10A, device isolation regions 41, celltransistors CT, peripheral transistors PT, bit line contacts (not shown)for connecting the drains of the cell transistors CT to the respectivebit lines, bit lines 47 and contact plugs 49 for connecting the sourcesof the cell transistors CT to the respective storage electrodes areformed on a silicon substrate 40 by using the schme that has beenexplained earlier with reference to FIG. 7A.

[0112] Then, as shown in FIG. 10B, a third interlayer insulating film45-3 is formed on a second interlayer insulating film 45-2 where thecontact plugs 49 are exposed. Then, openings 50 for forming cellcapacitors are formed in the third interlayer insulating film 45-3 byusing photolithography and RIE.

[0113] Next, as shown in FIG. 10C, a conductor such as SRO is depositedon the third interlayer insulating film 45-3 where the openings 50 areformed, thereby forming an SRO film. Then, those portions of the SROfilm which exclude what is located in the openings 50 are removed byusing CMP, for example. As a result, storage electrodes 2 of the SROfilm are formed in the openings 50.

[0114] Next, a high-dielectric substance such as BSTO or a ferroelectricsubstance is deposited on the third interlayer insulating film 45-3where the storage electrodes 2 are formed, thus forming the capacitorfilm 3 as shown in FIG. 10D. Then, a conductor such as SRO is depositedon the capacitor film 3, thereby forming the lower conductive layer 5.

[0115] Next, a conductor, such as aluminum, is deposited on the lowerconductive layer 5 by, for example, CVD, thereby forming the upperconductive layer 7 as shown in FIG. 10E. During this deposition,aluminum reacts with the SRO (lower conductive layer) 5 which is anoxide, thereby forming a barrier layer 6 of alumina (Al₂O₃) or the likeat the interface between the lower conductive layer 5, and the upperconductive layer 7.

[0116] Next, the upper conductive layer 7, the barrier layer 6 and thelower conductive layer 5 are etched at a time by using photolithographyand RIE, thus forming the plate electrode 4 as shown in FIG. 10F.Accordingly, the plate electrode 4 formed has a three-layer structure ofthe lower conductive layer 5., the barrier layer 6 and the upperconductive layer 7.

[0117] Then, a fourth interlayer insulating film 45-4 is formed on thethird interlayer insulating film 45-3 on which the plate electrode 4 isformed, as shown in FIG. 10G. Next, contact holes 51 which are connectedto the upper conductive layer 7 and contact holes 52 which are connectedto the interconnection layer (BL) 47 are formed in the fourth interlayerinsulating film 45-4 by using photolithography and RIE.

[0118] Next, as shown in FIG. 10H, titanium nitride (TiN) and titanium(Ti) are sequentially deposited on the fourth interlayer insulating film45-4 where the contact holes 51 and 52 are formed, thus forming a TiN/Tilamination film.. Then, those portions of this lamination film whichexclude the contact holes 51 and 52 are removed. As a result, contactplugs 53 and 54 of the TiN/Ti lamination film are respectively formed inthe contact holes 51 and 52.

[0119] Then, as shown in FIG. 9, titanium nitride (TiN) and titanium(Ti) are sequentially deposited on the fourth interlayer insulating film45-4 where the contact plugs 53 and 54 are formed, thus forming a TiN/Tilamination film. Then, this lamination film is removed by usingphotolithography and RIE, thus forming interconnection layers 55 and 56.

[0120] Thereafter, though no particular illustration is given, furthermultiple interconnection layers are formed and a passivation film ofsilicon nitride or silicon dioxide is formed finally. Then, hydrogenannealing is performed to adjust the characteristics of the celltransistors CT and the characteristics of the peripheral transistors PT,which completes the DRAM according to the third embodiment.

[0121] The DRAM according to the third embodiment can have the sameadvantages as the DRAM according to the second embodiment.

[0122] According to the fabrication method for the third embodiment, thebarrier layer 6 is formed by a reaction between the lower conductivelayer 5 and the upper conductive layer 7. This can eliminate a filmdeposition step to form the barrier layer 6 and can thus contribute tosuppressing a rise in the manufacturing cost.

[0123] As a modification of the third embodiment, a conductor such asaluminum is deposited on the lower conductive layer 5 of, for example,SRO or the like, thereby forming the upper conductive layer 7. Next, theupper conductive layer 7 and the lower conductive layer 5 are etched ata time by using photolithography and RIE, thus forming, first, the plateelectrode 4 which has a double-layer structure of the lower conductivelayer 5 and the upper conductive layer 7. Then, a heat treatment iscarried out to cause a reaction at the interface of SRO and aluminum,thereby forming the barrier layer 6 of alumina (Al₂O₃) or the like, sothat the plate electrode 4 finally has a three-layer structure of thelower conductive layer 5, the barrier layer 6 and the upper conductivelayer 7.

[0124] This fabrication method can eliminate a film deposition step toform the barrier layer 6 and can thus contribute to suppressing a risein the manufacturing cost. The fabrication method requires no etching ofthe barrier layer 6 at the time of carrying out an etching step offorming the pattern of the plate electrodes 4, thus facilitating theoverall etching process.

[0125] (Fourth Embodiment)

[0126]FIG. 11 is a cross-sectional view showing the cross sections of aDRAM cell array according to the fourth embodiment and a peripheralcircuit of the DRAM.

[0127] The DRAM according to the fourth embodiment illustrated in FIG.11 together with its manufacturing method will be described below.

[0128]FIGS. 12A through 12L are cross-sectional views illustrating theDRAM according to the fourth embodiment of this invention step by stepof main fabrication steps.

[0129] First, as shown in FIG. 12A, device isolation regions 41, celltransistors CT, peripheral transistors PT, bit line contacts (not shown)for connecting the drains of the cell transistors CT to the respectivebit lines, and bit lines 47 are formed on a silicon substrate 40 byusing the scheme that has been explained earlier with reference to FIG.7A. Then, a second interlayer insulating film 45-2 is formed on a firstinterlayer insulating film 45-1 where the bit lines 47 are formed.

[0130] Next, as shown in FIG. 12B, alumina or the like is deposited onthe second interlayer insulating film 45-2, thus forming a barrier film61. Then, contact holes 48 which reach the sources of the associatedcell transistors CT are formed in the barrier film 61, the secondinterlayer insulating film 45-2 and the first interlayer insulating film45-1. Then, contact plugs 49 are formed in the contact holes 48.

[0131] Then, as shown in FIG. 12C, a third interlayer insulating film45-3 is formed on the second interlayer insulating film 45-2 where thecontact plugs 49 are exposed. Then, alumina or the like is deposited onthe third interlayer insulating film 45-3, thus forming a barrier film62. Then, openings 50 for forming cell capacitors are formed in thebarrier film 62 and the third interlayer insulating film 45-3 by usingphotolithography and RIE.

[0132] Next, as shown in FIG. 12D, alumina or the like is deposited onthe third interlayer insulating film 45-3 where the openings 50 areformed, thus forming a barrier film 63. Then, the barrier film 63 isetched by RIE in such a way that the barrier film 63 remains on the sidewall of each opening 50.

[0133] Then, as shown in FIG. 12E, a conductor such as SRO is depositedon the barrier films 63 and 62, thereby forming an SRO film. Then, thoseportions of the SRO film which exclude what is located in the openings50 are removed by using CMP, for example. As a result, storageelectrodes 2 of the SRO film are formed in the openings 50.

[0134] Next, a high-dielectric substance such as BSTO or a ferroelectricsubstance is deposited on the storage electrodes 2 and the barrier film62, thus forming the capacitor film 3 as shown in FIG. 12F. Then, aconductor such as SRO is deposited on the capacitor film 3, therebyforming a lower conductive layer 5.

[0135] Next, as shown in FIG. 12G, alumina is deposited thin on thelower conductive layer 5, thus forming a barrier layer 6. At this time,the thickness of alumina that constitutes the barrier layer 6 is about 5nm and the film deposition is accomplished by sputtering in anatmosphere containing. oxygen, for example.

[0136] Then, a conductor such as aluminum is deposited on the barrierlayer 6 by sputtering, thus forming an upper conductive layer 7 as shownin FIG. 12H.

[0137] Next, the upper conductive layer 7, the barrier layer 6 and thelower conductive layer 5 are etched at a time by using photolithographyand RIE, thus forming the plate electrode 4 as shown in FIG. 12I.

[0138] Then, alumina is deposited on the third interlayer insulatingfilm 45-3 where the plate electrode 4 is formed, thereby forming abarrier film 64, as shown in FIG. 12J. Next, the barrier film 64 isetched by RIE so that the barrier film 64 remains on the side walls ofthe plate electrode 4. Accordingly, the capacitor structure which iscomprised of the storage electrode 2, the capacitor film 3 and the plateelectrode 4 is covered with the barrier films 61 to 64 and the barrierlayer 6, excluding the upper portions of the plug 49.

[0139] Then, a fourth interlayer insulating film 45-4 is formed on thethird interlayer insulating film 45-3 on which the plate electrode 4 andthe barrier film 65 are formed, as shown in FIG. 10G. Next, contactholes 51 which are connected to the upper conductive layer 7 and contactholes 52 which are connected to the interconnection layer (BL) 47 areformed in the fourth interlayer insulating film 45-4 by usingphotolithography and RIE.

[0140] Next, as shown in FIG. 12L, titanium nitride (TiN) and titanium(Ti) are sequentially deposited on the fourth interlayer insulating film45-4 where the contact holes 51 and 52 are formed, thus forming a TiN/Tilamination film. Then, those portions of this lamination film whichexclude the contact holes 51 and 52 are removed. As a result, contactplugs 53 and 54 of the TiN/Ti lamination film are respectively formed inthe contact holes 51 and 52.

[0141] Then, as shown in FIG. 11, titanium nitride (TiN) and titanium(Ti) are sequentially deposited on the fourth interlayer insulating film45-4 where the contact plugs 53 and 54 are formed, thus forming a TiN/Tilamination film. Then, this lamination film is removed by usingphotolithography and RIE, thus forming interconnection layers 55 and 56.

[0142] Thereafter, though no particular illustration is given, furthermultiple interconnection layers are formed and a passivation film ofsilicon nitride or silicon dioxide is formed finally. Then, hydrogenannealing is performed to adjust the characteristics of the celltransistors CT and the characteristics of the peripheral transistors PT,which completes the DRAM according to the fourth embodiment.

[0143] According to the DRAM of the fourth embodiment, the capacitorstructure is substantially covered with the barrier films 61 to 64(Al₂O₃) and the barrier layer 6 (Al₂O₃). Even if hydrogen annealing iscarried out after a multi-layer interconnection step, therefore, thebarrier films 61 to 64 (Al₂O₃) protect the capacitor film 3 (BSTO)against a reduction-originated damage. It is therefore possible tosuppress the degradation of the film quality of the capacitor film 3 andprevent the degradation of the capacitor characteristics, such as anincrease in leak current.

[0144] The above effect is further enhanced by combining the barrierfilms 61 to 64 (Al₂O₃) which cover at least a part of the capacitorstructure with the plate electrode 4 which has a three-layer structureof the lower conductive layer 5 (SRO), the barrier layer 6 (Al₂O₃) andthe upper conductive layer 7 (Al). This is because most of the portionaround the capacitor film 3 is covered with the barrier layer 6 and thebarrier films 61 to 64.

[0145] Although the first to fourth embodiments of this invention havebeen described above, this invention is not limited to those embodimentsbut may be modified in various other forms within the scope and spiritof the invention.

[0146] For instance, according to the second to fourth embodiments, thestacked capacitor is a “concave capacitor” wherein the storage electrode2 is formed into a concave shape along the opening 50 and the concavesurface is made to face the plate electrode 4, as shown in FIG. 13A.

[0147] The stacked capacitor may however be modified to be a “convexcapacitor” wherein the storage electrode 2 is formed into a convex shapeand the convex surface is made to face the plate electrode 4, as shownin FIG. 13B. Alternatively, the stacked capacitor may be modified to bea “cylindrical capacitor” as shown in FIG. 13C. The cylindricalcapacitor film is formed by forming the storage electrode 2 into aconcave shape along the opening 50 and then removing a part or all ofthe fourth interlayer insulating film 45-4 from that surface.

[0148] This invention is not limited to a stacked capacitor but may beadapted to a “planar capacitor” as well. One example of a “planarcapacitor” to which this invention is adapted is illustrated in FIG.13D. In the illustrated “planar capacitor”, the storage electrode isformed from a Ti layer 71, a TiN layer 72 and an SRO layer 73 which areformed in the silicon substrate 40. Then, the capacitor film (BSTO) isformed on the SRO layer 73 and the plate electrode 4 comprised of thelower conductive layer 5 (SRO), the barrier layer 6 (Al₂O₃) and theupper conductive layer 7 (Al) is formed on this capacitor film 3.

[0149] The capacitor structure according to this invention can beadapted to memory cells having a stacked gate structure which are usedin an EEPROM or the like as shown in FIG. 13E, as well as1-transistor-1-capacitor type DRAM or FRAM.

[0150] As shown in FIG. 13E, each memory cell having a stacked gatestructure comprises a gate insulating film 81 formed on the siliconsubstrate 40, a floating gate 82 formed on the gate insulating film 81and a control gate 84 which is capacitively coupled to the floating gate82 via a capacitor film 83.

[0151] When memory cells having a stacked gate structure are used in,for example, an EEPROM, there is a demand of making the capacitancebetween the floating gate 82 and the control gate 84 greater than thecapacitance between the floating gate 82 and the silicon substrate 40 inorder to improve the efficiency of injecting charges into the floatinggate 82. Therefore, a high-dielectric substance or ferroelectricsubstance which has a higher dielectric constant than a silicon oxidefilm or a silicon nitride film is likely to be used as the material forthe capacitor film 83. Examples of such a high-dielectric substance andferroelectric substance are (Ba,Sr)TiO₃ (generally, BSTO), BaTiO₃,SrTiO₃, Ta₂O₅, Pb(Zr,Ti)O₃ (generally, PZT), Pb(Nb,Ti)O₃, PbZrO₃,LiNbO₃, SrBi₂Ta₂O₉, SrBi₂(Ta,Nb)₂O₉ and Bi₄Ti₃O₁₃, which have alreadybeen discussed in the foregoing description of the first embodiment.

[0152] When such a high-dielectric substance or ferroelectric substanceis used for the capacitor film 83, the degradation of the film qualityshould be suppressed as much as possible because it leads to an increasein leak current, thus resulting in the deterioration of the chargeretaining characteristic.

[0153] In this respect, the gate insulating film 81 is formed of a metaloxide which contains at least one of metals Al, W, Cu, Ti, Co, Ta, Nb,Ru and Ir.

[0154] According to the memory cells having a stacked gate structure,when hydrogen annealing is performed, the gate insulating film 81protects the capacitor film 83 against a reduction-originated damage. Itis therefore possible to suppress the degradation of the film quality ofthe capacitor film 83 and prevent the degradation of the chargeretaining characteristics, such as an increase in leak current.

[0155] When the barrier layer 6 has an insulating property, thefollowing advantage can further be provided.

[0156] In the case of a DRAM of 265 Mbits, the cell array is groupedinto sub arrays of 256 kbits as shown in FIG. 14A. That is, the plateelectrode is segmented for every 256 kbits.

[0157] Under the situation shown in FIG. 14A, when one cell array, forexample, a cell array A, is accessed (for reading/writing), thepotential of the plate electrode in the cell array A slightlyfluctuates. This slight fluctuation becomes noise which is transmittedto the line that supplies the plate potential to the plate electrode.The nose transmitted to the line is transmitted to another plateelectrode which is directly connected via a line to the plate electrodein the cell array A, i.e., the plate electrode in the cell array B, theplate electrode in the cell array C and so forth. As a result, thepotentials of the plate electrodes in the unaccessed or inactive cellarrays B, C and so forth fluctuate. The fluctuation of the potentials ofthe plate electrodes may adversely affect the data retainingcharacteristics of cells.

[0158] When the capacitor structure has the barrier layer 6 which has aninsulating property, by way of contrast, the a capacitor is inserted inseries between the line for supplying the plate potential and the plateelectrode. The series-inserted capacitor absorbs a fluctuation of thepotential of the plate electrode in an accessed cell array, e.g., thecell array A. This makes the fluctuation of the potential of the plateelectrode in the cell array A hard to be transmitted to the line thatsupplies the plate potential, thus suppressing the fluctuation of thepotentials of the plate electrodes in the unaccessed cell arrays B, Cand so forth. It is thus possible to suppress the deterioration of thedata retaining characteristic of cells in unaccessed cell arrays.

[0159] Further, this structure has a resistance to other noise otherthan the one a memory cell generates at the time it is accessed. Evenwhen noise is applied to the line that supplies the plate potential, forexample, this noise is absorbed by the series-inserted capacitor. Thislikewise suppresses the fluctuation of the potential of the plateelectrode and thus restrains the deterioration of the data retainingcharacteristic of cells.

[0160] When the plate electrode is segmented for individual cell arrays,as apparent from the above, inserting the capacitor in series betweenthe line that supplies the plate potential and the plate electrode cansuppress the degradation in the data retaining characteristic which isoriginated from noise generated by a memory cell at the time it isaccessed or noise applied to the line that supplies the plate potential.

[0161] When there is one plate electrode, a capacitor should be insertedin series between the plate potential generating circuit 11 and theplate electrode. In this case, when noise is applied to the line thatsupplies the plate potential, particularly, the degradation in the dataretaining characteristic which is originated from this noise can besuppressed.

[0162] As apparent from the above, this invention can provide asemiconductor device whose structure can restrain the deterioration of adielectric film which constitutes a capacitor film even when annealingis performed in an atmosphere containing a reducing agent, and asemiconductor device having this capacitor.

[0163] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A semiconductor device comprising: a plurality ofdispersion electrodes formed in a dispersed manner above a semiconductorsubstrate; and a common electrode commonly facing said dispersionelectrodes via respective dielectric films and including a lowerconductive layer formed on said dielectric films, a barrier layer formedon said lower conductive layer and an upper conductive layer formed onsaid barrier layer.
 2. The semiconductor device according to claim 1,wherein each of said dispersion electrodes, each of said dielectricfilms and said lower conductive layer constitute a first capacitor, saidlower conductive layer, said barrier layer and said upper conductivelayer constitute a second capacitor, and a capacitance of said secondcapacitor is greater than that of said first capacitor.
 3. Thesemiconductor device according to claim 1, wherein said barrier layer isformed of a metal oxide.
 4. The semiconductor device according to claim3, wherein said metal oxide contains at least one of Ta, Al, W, Cu, Ti,Co, Nb, Ru and Ir.
 5. The semiconductor device according to claim 1,wherein said barrier layer is formed of a silicon nitride.
 6. Thesemiconductor device according to claim 1, wherein said dielectric filmsare formed of an oxide.
 7. The semiconductor device according to claim6, wherein said oxide contains at least one of (Ba,Sr)TiO₃, BaTiO₃,SrTiO₃, Ta₂O₅, Pb(Zr,Ti)O₃, Pb(Nb,Ti)O₃, PbZrO₃, LiNbO₃, SrBi₂Ta₂O₉,SrBi₂(Ta,Nb)₂O₉ and Bi₄Ti₃O₁₃.
 8. The semiconductor device according toclaim 1, wherein said lower conductive layer contains at least one ofPt, Ru, Re, Os, Rh, Ir, Fe, Mn, Cr, Co, Ni and Ti.
 9. The semiconductordevice according to claim 1, wherein said upper conductive layercontains at least one of Al, W, Cu, Ti, Co, Ta and Nb.
 10. Asemiconductor device comprising: one electrode formed above asemiconductor substrate; and an opposing electrode facing said oneelectrode via a dielectric film and including a lower conductive layerformed on said dielectric film, a barrier layer formed on said lowerconductive layer and an upper conductive layer formed on said barrierlayer.
 11. The semiconductor device according to claim 10, wherein anelectrical resistivity of said upper conductive layer is lower thanthose of said lower conductive layer and said barrier layer.
 12. Thesemiconductor device according to claim 10, wherein said barrier layeris formed of a metal oxide.
 13. The semiconductor device according toclaim 12, wherein said metal oxide contains at least one of Ta, Al, W,Cu, Ti, Co, Nb, Ru and Ir.
 14. The semiconductor device according toclaim 10, wherein said barrier layer is formed of a silicon nitride. 15.The semiconductor device according to claim 10, wherein said dielectricfilm is formed of an oxide.
 16. The semiconductor device according toclaim 15, wherein said oxide contains at least one of (Ba,Sr)TiO₃,BaTiO₃, SrTiO₃, Ta₂O₅, Pb(Zr,Ti)O₃, Pb(Nb,Ti)O₃, PbZrO₃, LiNbO₃,SrBi₂Ta₂O₉, SrBi₂(Ta,Nb)₂O₉ and Bi₄Ti₃O₁₃.
 17. The semiconductor deviceaccording to claim 10, wherein said lower conductive layer contains atleast one of Pt, Ru, Re, Os, Rh, Ir, Fe, Mn, Cr, Co, Ni and Ti.
 18. Thesemiconductor device according to claim 10, wherein said upperconductive layer contains at least one of Al, W, Cu, Ti, Co, Ta and Nb.19. A semiconductor device comprising: a capacitor structure formedabove a semiconductor substrate and including one electrode and anopposing electrode facing said one electrode via a dielectric film; anda barrier layer formed around said capacitor structure and substantiallycovering said capacitor structure.
 20. The semiconductor deviceaccording to claim 19, wherein said barrier layer is formed of a metaloxide.
 21. The semiconductor device according to claim 20, wherein saidmetal oxide contains at least one of Ta, Al, W, Cu, Ti, Co, Nb, Ru andIr.
 22. The semiconductor device according to claim 19, wherein saidbarrier layer is formed of a silicon nitride.
 23. The semiconductordevice according to claim 19, wherein said dielectric film is formed ofan oxide.
 24. The semiconductor device according to claim 23, whereinsaid oxide contains at least one of (Ba,Sr)TiO₃, BaTiO₃, SrTiO₃, Ta₂O₅,Pb(Zr,Ti)O₃, Pb(Nb,Ti)O₃, PbZrO₃, LiNbO₃, SrBi₂Ta₂O₉, SrBi₂(Ta,Nb)₂O₉and Bi₄Ti₃O₁₃.
 25. A semiconductor device comprising: a metal oxideformed on a semiconductor substrate; a first conductive film formed onsaid metal oxide; and a second conductive film facing said firstconductive film via a dielectric film.
 26. The semiconductor deviceaccording to claim 25, wherein said metal oxide contains at least one ofTa, Al, W, Cu, Ti, Co, Nb, Ru and Ir.
 27. The semiconductor deviceaccording to claim 25, wherein said dielectric film is formed of anoxide.
 28. The semiconductor device according to claim 27, wherein saidoxide contains at least one of (Ba,Sr)TiO₃, BaTiO₃, SrTiO₃, Ta₂O₅,Pb(Zr,Ti)O₃, Pb(Nb,Ti)O₃, PbZrO₃, LiNbO₃, SrBi₂Ta₂O₉, SrBi₂(Ta,Nb)₂O₉and Bi₄Ti₃O₃.
 29. A semiconductor device comprising: memory cells eachhaving a cell capacitor which includes a storage electrode and a plateelectrode facing said storage electrode via a dielectric film; a circuitfor generating a potential to be applied to said plate electrode; and acapacitor connected in series between an output terminal of said circuitand said plate electrode.
 30. A method of manufacturing a semiconductordevice comprising the steps of: forming one electrode above asemiconductor substrate; forming a dielectric film on said oneelectrode; forming a lower conductive layer on said dielectric film;forming a barrier layer on said lower conductive layer; forming an upperconductive layer on said barrier layer; and processing said upperconductive layer, said barrier layer and said lower conductive layer toform an opposing electrode including said upper conductive layer, saidbarrier layer and said lower conductive layer.